A full-parallel implementation of Self-Organizing Maps on hardware. (November 2021)

• Record Type: Journal Article
• Authors: Dias, Leonardo A.; Damasceno, Augusto M.P.; Gaura, Elena; Fernandes, Marcelo A.C.
• Is Part Of: Neural networks. Volume 143(2021)
• Page Start: 818
• Page End: 827
• Publication Date: 2021-11
• Subjects: Self-Organizing Map -- Parallel design -- Hardware -- FPGA; Neural computers -- Periodicals; Neural networks (Computer science) -- Periodicals; Neural networks (Neurobiology) -- Periodicals; Nervous System -- Periodicals; Ordinateurs neuronaux -- Périodiques; Réseaux neuronaux (Informatique) -- Périodiques; Réseaux neuronaux (Neurobiologie) -- Périodiques; Neural computers; Neural networks (Computer science); Neural networks (Neurobiology); Periodicals; 006.32
• DOI: 10.1016/j.neunet.2021.05.021
• Languages: English
• ISSNs: 0893-6080

Abstract

Abstract: Self-Organizing Maps (SOMs) are extensively used for data clustering and dimensionality reduction. However, if applications are to fully benefit from SOM based techniques, high-speed processing is demanding, given that data tends to be both highly dimensional and yet "big". Hence, a fully parallel architecture for the SOM is introduced to optimize the system's data processing time. Unlike most literature approaches, the architecture proposed here does not contain sequential steps — a common limiting factor for processing speed. The architecture was validated on FPGA and evaluated concerning hardware throughput and the use of resources. Comparisons to the state of the art show a speedup of 8 . 91 × over a partially serial implementation, using less than 15% of hardware resources available. Thus, the method proposed here points to a hardware architecture that will not be obsolete quickly.