A full-parallel implementation of Self-Organizing Maps on hardware. (November 2021) - Dias, Leonardo A.; Damasceno, Augusto M.P.; Gaura, Elena; Fernandes, Marcelo A.C.
Abstract: Self-Organizing Maps (SOMs) are extensively used for data clustering and dimensionality reduction. However, if applications are to fully benefit from SOM based techniques, high-speed processing is demanding, given that data tends to be both highly dimensional and yet "big". Hence, a fully parallel architecture for the SOM is introduced to optimize the system's data processing time. Unlike most literature approaches, the architecture proposed here does not contain sequential steps — a common limiting factor for processing speed. The architecture was validated on FPGA and evaluated concerning hardware throughput and the use of resources. Comparisons to the state of the art show a  speedup of 8 . 91 × over a partially serial implementation, using less than 15% of hardware resources available. Thus, the method proposed here points to a hardware architecture that will not be obsolete quickly.