(Invited) Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in FinFET, Stacked Nanowires and Monolithic 3D Integration. (20th July 2018)

• Record Type: Journal Article
• Authors: Porret, Clement; Hikavyy, Andriy Yakovitch; Gomez Granados, Juan Fernando; Baudot, Sylvain; Vohra, Anurag; Kunert, Bernardette; Douhard, Bastien; Bogdanowicz, Janusz; Schaekers, Marc; Kohen, David; Margetis, Joe; Tolle, John; Lima, Lucas; Sammak, Amir; Scappucci, Giordano; Rosseel, Erik; Langer, Robert; Loo, Roger
• Is Part Of: ECS transactions. Volume 86:Number 7(2018)
• Page Start: 163
• Page End: 175
• Publication Date: 2018-07-20
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/08607.0163ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.