(Invited) Factors Impacting Threshold Voltage in Advanced CMOS Integration: Gate Last (FINFET) vs. Gate First (FDSOI). (8th September 2015)

• Record Type: Journal Article
• Authors: Triyoso, Dina; Carter, Rick; Kluth, Jon; Luning, Scott; Child, Amy; Wahl, Jeremy; Mulfinger, Bob; Punchihewa, Kasun; Kumar, Anil; Kang, Laegu; Sporer, Ryan; Chen, Xiaobo; Straub, Sherry; Bohra, Girish; Patil, Suraj; Zhang, Xing; Chen, Alex; Togo, Mitsuhiro; Pal, Rohit
• Is Part Of: ECS transactions. Volume 69:Number 5(2015)
• Page Start: 103
• Page End: 110
• Publication Date: 2015-09-08
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/06905.0103ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : After decades of research, high-k metal gate has been successfully integrated into CMOS starting with the 45nm node. To continue scaling, the industry has chosen two integration approaches: FINFET with gate last and FDSOI with gate first. The FINFET with gate last integration was introduced into production at the 22nm node by Intel. The FDSOI with gate first integration was introduced into production at 28nm node by ST Microelectronics. There are some common factors impacting threshold voltage (Vt) on both integrations such as the high-k/metal gate film thickness and composition as well as the doping concentration. Beyond that, each integration approach has its own unique challenges that must be overcome to achieve targeted Vt and maintain Vt control. In this work we will highlight those unique challenges and discuss what knobs can be used to achieve the targeted Vt and maintain Vt control.