(Invited) Impact of the Metal Gate on the Oxide Stack Quality Assessed by Low-Frequency Noise. (1st August 2017)

• Record Type: Journal Article
• Authors: Simoen, Eddy; He, Liang; O'Sullivan, Barry; Veloso, Anabela; Horiguchi, Naoto; Collaert, Nadine; Claeys, Cor
• Is Part Of: ECS transactions. Volume 80:Number 4(2017)
• Page Start: 69
• Page End: 80
• Publication Date: 2017-08-01
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/08004.0069ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : A review is given about the impact of the metal gate (MG) in a High-k/Metal Gate (HKMG) stack on the quality and defectivity of the dielectric, assessed by low-frequency (LF) noise spectroscopy. In a first part, processing aspects are discussed, like, the thickness of the MG and the implementation of a gate-last approach. In the latter case, it is shown that both the cleaning (or dummy gate removal), the growth of the interfacial SiO2 layer (chemical versus thermal) and a post-HfO2 -deposition heat or SF6 plasma treatment need to be optimized for reducing the gate oxide trap density. In a second part, different MGs are compared from a viewpoint of noise magnitude. It is generally found that alternatives to the standard TiN gate yield better static and noise performance. Results will be presented both for scaled planar and FinFET technologies; the latter fabricated on either bulk or Silicon-on-Insulator (SOI) substrates. Also results on Gate-All-Around NanoWire FETs (GAA NWFETs) fabricated on SOI will be included.