Design of compact-diode-SCR with low-trigger voltage for full-chip ESD protection. (January 2023)

• Record Type: Journal Article
• Authors: Gao, Yuexin; Cai, Xiaowu; Han, Zhengsheng; Zeng, Chuanbin; Xia, Ruirui; Tang, Yun; Gao, Mali; Li, Bo
• Is Part Of: Microelectronics and reliability. Volume 140(2023)
• Publication Date: 2023-01
• Subjects: Full-chip ESD protection -- Silicon-controlled rectifier -- Transmission line pulse testing -- Turn-on time; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2022.114860
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: In this article, a compact-diode-silicon-controlled rectifier (CDSCR) for full-chip electrostatic discharge (ESD) protection is proposed and verified in 0.18 μm Silicon-on-Insulator (SOI) Bipolar-CMOS-DMOS (BCD) process. Intrinsic parasitic SCRs and diodes are employed as the main ESD paths, which greatly reduces area consumption. Besides, due to the RC- triggered circuit, low trigger voltage and short turn-on time are realized. With equivalent circuit and two-dimensional (2D) technology computer-aided design (TCAD) simulation, the operation principle and working mechanism are analyzed. In addition, transmission line pulse (TLP) and very fast TLP (VF-TLP) testing results show that the CDSCR could can endure human body model (HBM) pulse of 3420 V without latch-up issue and protect the chip effectively in charge device model (CDM) event. Furthermore, the proposed structure exhibits high current handing ability during ESD stress conditions and sufficiently low leakage current during normal circuit operating conditions. The CDSCR is conformed to provide full-chip ESD protection for 1.2 V application. Highlights: The CDSCR can achieve full-chip ESD protection and higher area efficiency. Employing SCRs and diodes as the main ESD paths, its' operation process is analyzed by TCAD simulation. Compared with other multi-mode ESD protection structures, the CDSCR can achieve higher HBM protection level of 3.42 V/μm 2 . In CDM events, the turn-on time of CDSCR is less than 1.65ns, which can effectively protect the chip. For 1.2 V operating voltage, the leakage current of CDSCR is less than 10 nA, which is suitable for low power application.