Improving graphene non‐volatile memory using self‐aligned gate. Issue 9 (4th April 2016)

• Record Type: Journal Article
• Authors: Lee, K.; Kim, O.
• Is Part Of: Electronics letters. Volume 52:Issue 9(2016)
• Page Start: 742
• Page End: 744
• Publication Date: 2016-04-04
• Subjects: graphene devices -- graphene -- random‐access storage; graphene nonvolatile memory -- channel resistance -- I‐V characteristics -- self‐aligned gate structure -- drain current -- transfer characteristics -- current 0.16 mA to 0.28 mA -- current 0.35 mA to 0.72 mA -- voltage 8.5 V -- voltage 6.7 V -- C; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2015.4274
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : As the scale of graphene‐based non‐volatile memory is reduced, the ratio of access resistance R A to total channel resistance R TOT is increased. To investigate the effect of the R A on I–V characteristics, we fabricated devices with various access lengths L A and self‐aligned structure. Proposed structure using self‐aligned gate minimises L A, and thereby improves the drain current, 'on/off' current ratio I ON / I OFF and transfer characteristics. In proposed structure, 'off' current is increased from 0.16 to 0.28 mA because R TOT was reduced; 'on' current increased from 0.35 to 0.72 mA, but I ON / I OFF increased from 2.18 to 2.57. Proposed structure also had larger memory window (8.5 V) than did conventional devices (6.7 V).