Characterization and modeling of drain lag using a modified RC network in the ASM-HEMT framework. (January 2023)

• Record Type: Journal Article
• Authors: Nazir, Mohammad Sajid; Pampori, Ahtisham; Dangi, Raghvendra; Kushwaha, Pragya; Yadav, Ekta; Sinha, Santanu; Chauhan, Yogesh Singh
• Is Part Of: Solid-state electronics. Volume 199(2023)
• Publication Date: 2023-01
• Subjects: Advanced SPICE model (ASM) HEMT model -- AlGaN/GaN high electron mobility transistor (HEMT) -- Current degradation (CD) -- Dynamic RON -- Drain lag -- Gate lag -- Parasitic backgate -- n2Deg; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2022.108490
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: Gallium-Nitride High Electron Mobility Transistors (GaN-HEMTs) are susceptible to trapping effects, significantly degrading device performance. The degradation can be seen in the current–voltage characteristics and also manifests in the form of a shift in the dynamic on-resistance and threshold voltage. In this paper, we present pulsed characterization and empirical modeling of a 250 × 10 μ m RF GaN HEMT device. To study the impact of drain-induced trapping, pulse I-V characterization is performed at a fixed quiescent gate voltage of −7 V with varying drain quiescent voltage. An empirical RC network approach is proposed to accurately model the trapping in the device. The model effectively captures the impact of trapping and takes into account the self-limiting behavior of traps. The model is implemented in Verilog-A within the Advanced SPICE Model for High Electron Mobility Transistors (ASM-HEMT) framework. Validation of the model is done with six different quiescent conditions of pulse measurement with on-state drain bias varying from 0 V to 20 V. Highlights: Dual Pulse and Drain current Transient measurements are performed. Device is characterized for drain lag under multiple quiescent condition. Drain lag, as well as Gate lag, is observed even though Gate quiescent bias is fixed gate quiescent ( V G S Q ) of −7 V with varying drain quiescent bias. An empirical RC network approach is proposed to accurately model the trapping in the device. The model is implemented in Verilog-A within the ASM-HEMT framework.