A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. (December 2022)

• Record Type: Journal Article
• Authors: Lai, Mingche; Zhang, Geng; Lv, Fangxu; Zheng, Xuqiang; Wang, Heming; Lv, Dongbin; Xu, Chaolong; Qi, Xingyun
• Is Part Of: Microelectronics journal. Volume 130(2022)
• Publication Date: 2022-12
• Subjects: Wireline transceiver -- Chiplet -- Correlated non-return-to-zero (CNRZ) -- Continuous time linear equalizer (CTLE) -- Forwarded clock -- Clock and data alignment (CDA) -- Phase interpolator (PI); Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105628
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents a low-power, high-bandwidth wireline transceiver for chiplet. The transceiver uses a new technology of correlated non-return to zero (CNRZ) to improve the pin efficiency and reduce the noise of the common mode and crosstalk (CMN and XTALK). The transmitter adopts a 4:1 multiplexer (MUX) and a special voltage-mode driver [source series terminated (SST)] to improve the power efficiency. The receiver utilizes a low jitter clock-and-data alignment (CDA) based on high resolution phase interpolator (PI) and a MINI-PLL with differential filter based to improve the jitter performance of the receiver's clock. In addition, a special continuous-time linear equalizer (CTLE) is introduced into the multiple-input compare (MIC) based decode circuit to reduce the receiver's bit error rate (BER). This transceiver is designed with a 28 nm CMOS process technology and supplied with 0.9/1.2 V. Simulation results show that this transceiver can operate at 200 Gb/s with the 33.3 Gb/s single-wire data rate and a power consumption of 1.06 pJ/b. The transceiver's BER is less than 1E-15 and eye-wide-opening is 12.02 ps (48.08% UI), which is under 10 dB channel loss at 20 GHz Nyquist frequency.