Plasma-enhanced atomic layer deposition of amorphous Ga2O3 gate dielectrics. (November 2022)

• Record Type: Journal Article
• Authors: Badali, Yosef; Arslan, Engin; Ulusoy Ghobadi, Turkan Gamze; Ozcelik, Suleyman; Ozbay, Ekmel
• Is Part Of: Journal of physics and chemistry of solids. Volume 170(2022)
• Publication Date: 2022-11
• Subjects: Atomic layer deposition -- Amorphous Ga2O3 -- Dielectric properties -- Interface traps; Solids -- Periodicals; Solides -- Périodiques; Solids; Periodicals; 530.41
• DOI: 10.1016/j.jpcs.2022.110976
• Languages: English
• ISSNs: 0022-3697

Abstract

Abstract: Amorphous gallium oxide (Ga2 O3 ) thin films were investigated as gate dielectrics for electronic device applications using plasma-enhanced atomic layer deposition. The structural and morphological properties as well as the electrical and dielectric behaviors of Ga2 O3 thin films were explored. The surface morphology of the amorphous Ga2 O3 thin film was highly smooth with root mean square of 0.55 nm and low defect density, which were visible to atomic force microscopy. The grazing incidence X-ray diffraction pattern showed no discernible peak, indicating that the film was amorphous. The X-ray photoelectron spectroscopy depth-profiling analysis showed that the Ga/O ratio was 0.76, slightly more than the optimum 2/3 ratio (0.67). The temperature-dependent current–voltage characteristics of the Au/Ni/Ga2 O3 /p-Si structure revealed that ideality factor and barrier height values decreased and increased with increasing temperature, respectively, demonstrating their high temperature dependency. Regardless of the applied frequency, Ga2 O3 thin films exhibited a good dielectric constant of about ∼9 at zero bias voltage. The comprehensive capacitance–voltage analysis showed low trap densities of about 10 12 eV −1 cm −2 at the Ga2 O3 –p-Si interface. Highlights: Amorphous gallium oxide (Ga2 O3 ) thin films were coated using plasma-enhanced atomic layer deposition (PEALD). The charge-transport mechanisms of this structure were studied via temperature-dependent current-voltage ( I–V ) measurement. The dielectric behavior of the fabricated MOS structure was explored using frequency-dependent capacitance-voltage ( C–V ) and conductance-voltage ( G/ω − V ) experiments. The interface trap density (Dit ) was estimated using the admittance spectroscopy method at room temperature.