A 16-bit 1 MSPS SAR ADC with foreground calibration and residual voltage shift strategy. (December 2020)

• Record Type: Journal Article
• Authors: Zhang, Xian; Cao, Xiaodong; Zhang, Xuelian
• Is Part Of: Journal of semiconductors. Volume 41:Number 12(2020)
• Publication Date: 2020-12
• Subjects: foreground all-digital calibration -- RS strategy -- RS-based dither -- auto-zero comparator -- SAR ADC; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1674-4926/41/12/122401
• Languages: English
• ISSNs: 1674-4926

Abstract

Abstract: In this paper, a 16-bit 1MSPS foreground calibration successive approximation register analog-to-digital converter (SAR ADC) is developed by the CMOS 0.25 μ m process. An on-chip all-digital foreground weights calibration technique integrating self-calibration weight measurement with PN port auto-balance technique is designed to improve the performance and lower the costs of the developed SAR ADC. The SAR ADC has a chip area of 2.7 × 2.4 mm 2, and consumes only 100 μ W at the 2.5 V supply voltage with 100 KSPS. The INL and DNL are both less than 0.5 LSB.