Analysis of back-gate bias impact on 22 nm FDSOI SRAM cell. (October 2022)

• Record Type: Journal Article
• Authors: lv, Yinghuan; Ge, Hao; Xie, Tiantian; Ren, Zhipeng; Chen, Jing
• Is Part Of: Solid-state electronics. Volume 196(2022)
• Publication Date: 2022-10
• Subjects: SRAM -- FDSOI -- Back-gate bias combination; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2022.108418
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: The back-gate terminal biasing has been used to improve the SRAM cells' performance. In this paper, the impact of back-gate bias on the performance of 22 nm FDSOI SRAM 6T cell is analyzed. The cell is fabricated in the regular well and two back-gate terminals are connected to Pwell and Nwell, respectively. The influences of back-gate bias on the cell are studied by the variations of the metrics of leakage current, read current, static noise margin (SNM) and N -curve under the three back-gate bias combinations. Through measurements and HSPICE simulations, the mechanism of the variations of the cell metrics caused by the changes of the back-gate bias is explained by the shift of electrical characteristics of transistors inside the cell.