A physics-based drain current model for Si1-xGex source/drain NT JLFET for enhanced hot carrier reliability with temperature measurement. (August 2022)

• Record Type: Journal Article
• Authors: Thakur, Anchal; Dhiman, Rohit
• Is Part Of: Microelectronics journal. Volume 126(2022)
• Publication Date: 2022-08
• Subjects: Gate–induced drain leakage -- Junctionless transistor -- SiGe source/drain -- L-BTBT -- Nanotube -- Short channel effects (SCEs); Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105501
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In this paper, we report, the hot carrier reliability issue in the Si1- x Ge x source/drain nanotube (NT) junctionless field-effect transistor (JLFET) with temperature variations. The surface potential, electric field and drain current have been formulated by developing a physics-based analytical model. SiGe in the source/drain regions creates valence band discontinuity of Δ E g = 0.23 eV which significantly increases the tunneling width at the channel/drain interface and therefore, results in a diminished L-BTBT action. The results demonstrate that at T = 500 K, drain current with the influence of interface trap charges in the Si1- x Ge x S/D architecture shows better immunity than the conventional NTJLFET. The Si1- x Ge x S/D enhances the reliability of analog/RF parameters such as transconductance ( g m ), intrinsic gain ( g m / g d ), cut-off frequency ( f T ), and gain-transconductance-frequency-product (GTFP), against the hot carriers. We have also explored the reliability with germanium (Ge) content, x and observed that for Ge content above x = 0.3, the reliability degrades in terms of higher electron temperature, reduced g m, and lower f T . The analytical results are verified and are in good agreement with results of Sentaurus TCAD simulations. The Si1– x Ge x S/D architecture combined with NT core gate can help relieve the HCI trap charge reliability for JLFETs leading to significantly improved analog/RF parameters. Highlights: To precisely address the issue of hot carrier induced interface charges with the temperature, a physics-based temperature dependent analytical model for the surface potential and drain current has been developed. The inclusion of SiGe in the source and drain regions can enhance the reliability of NTJLFETs against the impact of hot charge carriers at higher temperatures. In the SiGe S/D NTJLFET, at T = 500 K, g m is increased by 4.5% and decreased by 5.1% for the positive and negative trap charges respectively with respect to undamaged device, while in the conventional NTJLFET, it is enhanced and reduced by 14.2% and 28.57%.