Test architecture optimization algorithms for coarse-grain partitioned 3D system-on-chip. (July 2022)

• Record Type: Journal Article
• Authors: Vohra, Harpreet; Singh, Amardeep
• Is Part Of: Computers & electrical engineering. Volume 101(2022)
• Publication Date: 2022-07
• Subjects: Testing -- 3D system-on-chip testing -- DFT architecture -- Test infrastructure; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2022.108049
• Languages: English
• ISSNs: 0045-7906

Abstract

Highlights: The critical contributions of the proposed test solution development technique include. Development of an integrated modular core-based test solution for the coarse grain partitioned 3D SoC. Optimization of test architecture of individual die and complete stack on the basis of allowed intractability. Minimization of the test cost in terms of testing time, test power, and Through Silicon Via requirements. Support of pre, partial, and post bond testing. Abstract: The occurrence of manufacturing defects in complex 3D System-on-Chip can affect their performance and functionality. Massive test data is required to test such systems, which increases testing time. This paper presents an efficient heuristic-based solution that addresses test architecture development for both fixed and flexible design scenarios in coarse-grain partitioned 3D Systems-on-Chip. The algorithm minimizes the test times at inter and intra die levels while addressing the various constraints. It works in two stages: initially, it prepares a tentative test architecture for individual dies with fixed test widths. Later, a solution for the allotment of the test wires to separate dies is made such that the test time of the complete stack reduces. Experiments performed using different ITC'02 SoC benchmark circuits show the effectiveness of the proposed solutions. The resultant test time is comparable to the lower bounds of test time of the complete 2D benchmark. Graphical abstract: Image, graphical abstract