Design of a power-efficient Kogge–Stone adder by exploring new OR gate in 45nm CMOS process. Issue 4 (23rd March 2020)

• Record Type: Journal Article
• Authors: John, Vimukth; Sam, Shylu; Radha, S.; Paul, P. Sam; Samuel, Joel
• Is Part Of: Circuit world. Volume 46:Issue 4(2020)
• Page Start: 257
• Page End: 269
• Publication Date: 2020-03-23
• Subjects: Kogge–Stone adder -- Transistor sizing -- Low power -- XOR logic -- OR logic -- Power delay product (PDP) -- Energy -- Circuit Implementation -- Circuit simulation; Electronic circuits -- Design and construction -- Periodicals; Electronic circuits -- Periodicals; 621.381505
• DOI: 10.1108/CW-12-2018-0104
• Languages: English
• ISSNs: 0305-6120

Abstract

Abstract : Purpose: The purpose of this work is to reduce the power consumption of KSA and to improve the PDP for data path applications. In digital Very Large – Scale Integration systems, the addition of two numbers is one of the essential functions. This arithmetic function is used in the modern digital signal processors and microprocessors. The operating speed of these processors depends on the computation of the arithmetic function. The speed computation block for most of the datapath elements was adders. In this paper, the Kogge–Stone adder (KSA) is designed using XOR, AND and proposed OR gates. The proposed OR gate has less power consumption due to the less number of transistors. In arithmetic logic circuit power, delay and power delay products (PDP) are considered as the important parameters. The delays reported for the proposed OR gate are less when compared with the conventional Complementary Metal Oxide Semiconductor (CMOS) OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. To analyze the performance of KSA, extensive Cadence Virtuoso simulations are used. From the simulation results based on 45 nm CMOS process, it was observed that the proposed design has obtained 688.3 nW of power consumption, 0.81 ns of delay and 0.55 fJ of PDP at 1.1 V. Design/methodology/approach: In this paper, a new circuit for OR gate is proposed. The KSA is designed using XOR, AND and proposed OR gates. Findings: The proposed OR gate has less power consumption due to the less number of transistors. The delays reported for the proposed OR gate are less when compared with the conventional CMOS OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. Originality/value: In arithmetic logic circuit power, delay and PDP are considered as the important parameters. In this paper, a new circuit for OR gate is proposed. The power consumption of the designed KSA using the proposed OR gate is very less when compared with the conventional KSA. Simulation results show that the performance of the proposed KSA are improved and suitable for high speed applications.