Differential spin Hall MRAM based low power logic circuits and multipliers. (1st July 2022)

• Record Type: Journal Article
• Authors: Nehra, Vikas; Prajapati, Sanjay; Kumar, T Nandha; Kaushik, Brajesh Kumar
• Is Part Of: Semiconductor science and technology. Volume 37:Number 7(2022)
• Publication Date: 2022-07-01
• Subjects: hybrid CMOS/MTJ circuit -- magnetic tunnel junction (MTJ) -- multiplier -- spintronics -- spin-transfer torque (STT)-MRAM -- spin-orbit torque (SOT)-MRAM; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1361-6641/ac6d70
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: A Multiplier is an essential component that dictates the performance of modern computing systems. However, high power dissipation of complementary metal-oxide semiconductor (CMOS) multiplier circuits has become a major concern in sub 45 nm technology nodes. Recently, emerging non-volatile memory based hybrid circuits have gained a lot of attention due to the prominent feature of negligible static power consumption. Magnetic tunnel junction (MTJ) based spin-torque memories have been used for low power applications. However, spin-transfer torque magnetic random-access memory (STT-MRAM) based hybrid CMOS/MTJ circuits exhibit higher write energy and longer incubation delay. In this work, a differential spin Hall (DSH)-MRAM cell is employed for logic and circuit applications. It stores a pair of complementary bits with low write voltage and reduced area. The variability analysis of DSH-MRAM signifies the availability of sufficient margin between different resistance states. Different types of 8 × 8 and 4 × 4 hybrid CMOS/MTJ multipliers are analyzed using DSH based adders and logic gates. The proposed multipliers consume approximately 20% less power and exhibit 19% improvement in power-delay product characteristics compared to CMOS based multipliers.