Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K. (August 2022)

• Record Type: Journal Article
• Authors: Mariniello, Genaro; Barraud, Sylvain; Vinet, Maud; Cassé, Mikael; Faynot, Olivier; Calcade, Jaime; Antonio Pavanello, Marcelo
• Is Part Of: Solid-state electronics. Volume 194(2022)
• Publication Date: 2022-08
• Subjects: Vertically stacked nanowires -- High temperature -- DIBL; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2022.108337
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: The impact higher temperatures are noticed by the increase of Ioff and the decrease of Ion, on stacked vertically nanowire devices. The reduction of μr reverberates on the IDS /(W/L) degradation with the increasing of temperature. VGS, ZTC on vertically stacked nanowire devices are clearly visible until 550 K, for all devices, maintaining VGS around 0.9 V. DIBL is more impacted for high temperatures and wider devices. Abstract: This paper aims at analyzing the electrical characteristics of n-type vertically stacked nanowires with variable fin width, operating in the temperature range of 300–600 K. Basic electrical parameters, such as threshold voltage, subthreshold slope, and carrier mobility are extracted in the linear region, whereas the transconductance, output conductance, and intrinsic voltage gain are extracted in saturation, to access some of device's analog figures of merit. Also, it has been analyzed the DIBL, GIDL, Ion, and Ioff. currents.