IMSC: Instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructions. (9th March 2022)

• Record Type: Journal Article
• Authors: Wang, Yuze; Liu, Peng; Jiang, Yingtao
• Is Part Of: IET information security. Volume 16:Number 4(2022)
• Page Start: 314
• Page End: 319
• Publication Date: 2022-03-09
• Subjects: instruction sets -- trusted computing; Computer security -- Periodicals; Cryptography -- Periodicals; Computer networks -- Security measures -- Periodicals; Database security -- Periodicals; 005.8
• DOI: 10.1049/ise2.12059
• Languages: English
• ISSNs: 1751-8709

Abstract

Abstract: A secure processor requires that no secret, undocumented instructions be executed. Unfortunately, as today's processor design and supply chain are increasingly complex, undocumented instructions that can execute some specific functions can still be secretly introduced into the processor system as flaws or vulnerabilities. To address this problem that may cause potentially serious security breaches, the instruction set architecture (ISA) monitor and secure cache (IMSC) is proposed. As a lightweight solution, IMSC employs an ISA monitor to discover and correct any potential threats imposed by undocumented instructions, and it relies on a secure cache to ensure the credibility of the system. The authors' case studies have confirmed that IMSC can effectively protect a processor system from being exploited by undocumented instructions and thus provide a trustworthy computing environment, all at low hardware and run‐time costs.