Double-node-upset aware SRAM bit-cell for aerospace applications. (June 2022)

• Record Type: Journal Article
• Authors: Prasad, Govind; Mandi, Bipin Chandra; Ali, Maifuz
• Is Part Of: Microelectronics and reliability. Volume 133(2022)
• Publication Date: 2022-06
• Subjects: Aerospace applications -- Critical charge -- Low power -- Soft errors -- SRAM -- Stability; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2022.114526
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: In aerospace applications, the continuous scaling of CMOS technology makes SRAM cells more and more susceptible to soft errors. To overcome this issue, a radiation-hardened-based (RHBD) 13T SRAM cell has been proposed in this paper. The proposed cell has several benefits over other standard RHBD cells. The proposed cell can not only recover from SNUs induced at any of its sensitive nodes but also from DNUs induced at any of its sensitive node pairs. It has the lowest hold, total power cost, the highest critical charge, moderate area overhead, and better stability. To improve speed, the proposed cell uses a unique feedback path among its internal nodes. Finally, the figure of merit (FOM), SNU probability of failure (POF) comparison of cells validate that the proposed cell is a better choice for sub-nanometer aerospace applications. Highlights: In aerospace applications, the continuous scaling of CMOS technology makes SRAM cells more and more susceptible to soft errors. To overcome this issue, a radiation-hardened-based (RHBD) 13T SRAM cell has been proposed in this paper. The proposed cell can self-recover at all the sensitive node pairs from all the possible DNUs of both polarities. The proposed cell dissipates the lowest hold and total power cost due to stacked structure and weak PMOS transistors in the pull-down path. The write and read speed are also improved compared to other cells due to lower body effect, feedback path, and extra access transistors (N5).