Performance investigation of Reconfigurable–FET under the influence of parameter variability of ferroelectric gate stack at high temperatures. (June 2022)

• Record Type: Journal Article
• Authors: Pandey, Priyanka; Kaur, Harsupreet
• Is Part Of: Microelectronics journal. Volume 124(2022)
• Publication Date: 2022-06
• Subjects: Ferroelectric parameters -- Hysteresis -- Negative capacitance -- Reconfigurable FET -- Temperature -- Variation; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105442
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract : In the present work, a detailed study is presented to investigate the impact of variations in material parameters such as remnant polarization ( P R ), coercive field ( E C ) of the ferroelectric layer that constitutes the gate stack of negative capacitance–reconfigurable–FET (NC-R-FET). The analysis is carried over a broad temperature range to extensively investigate the impact of these variations on device performance at elevated temperatures as well. A dual-gate NC-R-FET can result in significant improvement in terms of enhanced drive current along with super steep switching characteristics. However, any unintended variation caused in ferroelectric (FE) parameters can significantly affect device performance such as decrease in gain, degradation in subthreshold swing and current drivability and this scenario can be particularly critical if device operation becomes hysteretic. Thus, in the present work, the influence of these unintended variations on the device performance of NC-R-FET is exhaustively studied over a broad temperature range.