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MLA Citation
D. Issartel et al.. “Architecture optimization of SPAD integrated in 28 nm FD-SOI CMOS technology to reduce the DCR.” Solid-state electronics, vol. 191, 2022, p. . http://access.bl.uk/ark:/81055/vdc_100153432841.0x000058
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D. Issartel et al.. “Architecture optimization of SPAD integrated in 28 nm FD-SOI CMOS technology to reduce the DCR.” Solid-state electronics, vol. 191, 2022, p. . http://access.bl.uk/ark:/81055/vdc_100153432841.0x000058