Cite
HARVARD Citation
Issartel, D. et al. (2022). Architecture optimization of SPAD integrated in 28 nm FD-SOI CMOS technology to reduce the DCR. Solid-state electronics. p. . [Online].
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Issartel, D. et al. (2022). Architecture optimization of SPAD integrated in 28 nm FD-SOI CMOS technology to reduce the DCR. Solid-state electronics. p. . [Online].