Cite
HARVARD Citation
Sathishkumar, M. et al. (2022). Performance evaluation of gate engineered InAs–Si heterojunction surrounding gate TFET. Superlattices and microstructures. p. . [Online].
This is an interim version of our Electronic Legal Deposit Catalogue-eJournals and eBooks while we continue to recover from a cyber-attack.
Sathishkumar, M. et al. (2022). Performance evaluation of gate engineered InAs–Si heterojunction surrounding gate TFET. Superlattices and microstructures. p. . [Online].