Cite
HARVARD Citation
Parekh, P. et al. (2021). Gated Vernier delay line time integrator with applications in ΔΣ time-to-digital converter. Microelectronics journal. p. . [Online].
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Parekh, P. et al. (2021). Gated Vernier delay line time integrator with applications in ΔΣ time-to-digital converter. Microelectronics journal. p. . [Online].