Gated Vernier delay line time integrator with applications in ΔΣ time-to-digital converter. (January 2022)

• Record Type: Journal Article
• Authors: Parekh, Parth; Yuan, Fei; Zhou, Yushi
• Is Part Of: Microelectronics journal. Volume 119(2021)
• Publication Date: 2022-01
• Subjects: Time-mode signal processing -- Time-to-digital converters -- Time integrator -- Gated Vernier delay line time integrator; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105316
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: An all-digital bi-directional gated Vernier delay line (BDGVDL) time integrator with applications in all-digital Δ Σ time-to-digital converters (TDCs) is presented. The configuration and operation of the proposed Vernier time integrator are presented and its nonlinearity is analyzed. An in-depth treatment of the timing error of the time integrator due to supply, thermal, and flicker noise is provided. Design considerations including the impact of the latency and metastability of catch-detect DFFs are examined. The proposed time integrator is utilized in design of an all-digital single-bit Δ Σ TDC. Simulation results in both time and frequency domains confirm that the time integrator performs time integration and the gain of the integrator obtained in simulation agrees with that obtained from theoretical analysis. The TDC exhibits first-order noise-shaping with noise floor independent of the amplitude of the input. The dynamic range of the TDC is lower-bound by the difference between the per-stage-delay of the slow and fast lines and the nonlinearity of the delay stages of the time integrator and upper-bound by the number of the delay stages of the time integrator.