A physical insight into variation aware minimum VDD for deep subthreshold operation of FinFET. (25th October 2021)

• Record Type: Journal Article
• Authors: Yadav, Sarita; Chauhan, Nitanshu; Tyagi, Shobhit; Sharma, Arvind; Banchhor, Shashank; Joshi, Rajiv; Pratap, Rajendra; Bulusu, Anand
• Is Part Of: Semiconductor science and technology. Volume 36:Number 12(2021)
• Publication Date: 2021-10-25
• Subjects: FinFET extension length -- fundamental limits -- inverter -- minimum voltage supply -- sub-threshold operation -- temperature variability -- ultra-low voltage FinFET logic; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1361-6641/ac2d0f
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: Several ultra-low power applications, that do not require high performance, can benefit from operation at the lowest possible supply voltage. Scaling of supply voltage is an effective method to reduce the energy consumption in digital circuits. The fundamental limit for supply voltage has been established as 36 mV for planar complementary metal oxide semiconductor (CMOS) circuits based on Shannon's channel capacity theorem. Owing to its near ideal sub-threshold characteristics, fin field effect transistor (FinFET) devices are a better fit for ultra-low voltage applications than planar devices. In this work, the fundamental limit on supply voltage for FinFET based logic circuits has been established for the first time. This theoretical limit is found to be significantly lower than the limit for planar CMOS circuits. The effect of variation of temperature and device design parameters on this fundamental limit is also explored. The analysis is extended to other logic gates such as NAND gate. Since the operation of a FinFET device in the ultra-low voltage domain is quite different from its planar counterpart, a novel physics based, semi-empirical current equation valid for supply voltage below 100 mV has been proposed for a FinFET device to calculate this fundamental limit. Such a current model is of great importance to a circuit designer because of the ease it offers for the back of the envelope calculations. The logic gates operating in this regime are then analyzed using this proposed model.