Benefits of using arrays of vertical nanowire FETs in integrated circuits to mitigate variability. (12th November 2021)

• Record Type: Journal Article
• Authors: del Moral, A; Amat, E; Bausells, J; Perez-Murano, F
• Is Part Of: Semiconductor science and technology. Volume 36:Number 12(2021)
• Publication Date: 2021-11-12
• Subjects: vertical nanowire -- 3D TCAD -- variability -- gate-all-around devices; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1361-6641/ac3371
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: We investigate the benefits of the use of arrays of vertical nanowire (vNW) field-effect transistors (FETs) to implement integrated circuits. By means of technology computer aided design and circuit simulations, the optimal dimensions of the vNWFETs are determined. Device and circuit variability levels have been investigated. The benefits of using array configurations are the decrease of the response time and a significant mitigation of the variability level as the number of the elements in the array increases.