Low frequency noise performance of horizontal, stacked and vertical silicon nanowire MOSFETs. (October 2021)

• Record Type: Journal Article
• Authors: Simoen, Eddy; de Oliveira, Alberto Vinicius; Agopian, Paula Ghedini Der; Ritzenthaler, Romain; Mertens, Hans; Horiguchi, Naoto; Martino, Joao Antonio; Claeys, Cor; Veloso, Anabela
• Is Part Of: Solid-state electronics. Volume 184(2021)
• Publication Date: 2021-10
• Subjects: Gate-All-Around -- Nanowires -- Nanosheets -- Low-frequency noise -- Silicon MOSFETs; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2021.108087
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: LF noise in 3 generations of silicon nanowire transistors. New results in vertical NW transistors. Impact of gate stack processing on the 1/f noise magnitude. Abstract: The low frequency noise performance of Gate-All-Around Nanowire (NW) or Nanosheet (NS) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is investigated, taking account of the impact of the device architecture, i.e., junctionless (JL) versus inversion-mode (IM) and process variations for the gate metal. The horizontal devices are characterized by 1/f noise, dominated by the number fluctuation mechanism, so that the power spectral density (PSD) is directly proportional with the trap density in the gate stack. The average 1/f noise PSD is becoming smaller going from single NW transistors on Silicon-on-Insulator substrates, to stacked horizontal NS devices on bulk silicon and, finally, vertical NWFETs with a substrate source contact. At low currents and frequencies below 1 kHz the 1/f noise in the vertical NWs is, in contrast to the horizontal devices, controlled by mobility fluctuations. In these devices white noise is observed above 1 kHz.