A simple test structure for the electrical characterization of front and back channels for advanced SOI technology development. (November 2021)

• Record Type: Journal Article
• Authors: Alepidis, M.; Ionica, I.; Milesi, F.; Bresson, N.; Gaudin, G.; Cristoloveanu, S.; Reboh, S.
• Is Part Of: Solid-state electronics. Volume 185(2021)
• Publication Date: 2021-11
• Subjects: Fully depleted SOI -- Double-gate MOSFET -- Pseudo-MOSFET -- Parameter extraction -- Doped/undoped contacts; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2021.108047
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: Double gate structures for channel material and gate stack characterization. Easy and simple techniques based on the pseudo-MSOFET configuration. Fast fabrication loop of double gate MOSFET. Test structures for parameter extraction. Double-gate pseudo-MOSFET for rapid material characterization. Abstract: Pseudo-MOSFET delivers a fast, simple and reliable way of characterizing electrically SOI substrates without the need of full CMOS fabrication. However, the information refers to the back interface. Here, to probe the front interface, we extend the concept to a double-gate pseudo-MOSFET. The structure provides a pertinent test vehicle for the characterization and development of transistors channel and gate stack materials in a configuration similar to fully fabricated transistors. We show that the devices with undoped terminals need specialized modeling development to describe the double gate effect. Devices with doped terminals are immediately exploitable for parameter extraction.