III-V-on-Si transistor technologies: Performance boosters and integration. (November 2021)

• Record Type: Journal Article
• Authors: Caimi, D.; Schmid, H.; Morf, T.; Mueller, P.; Sousa, M.; Moselund, K.E.; Zota, C.B.
• Is Part Of: Solid-state electronics. Volume 185(2021)
• Publication Date: 2021-11
• Subjects: MOSFETs -- TFETs -- Integration -- RF -- CMOS -- Cryogenic electronics; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2021.108077
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: Integration of III-V materials on SI substrates key to enable commercial viability. Direct wafer bonding is a promising III-V integration technique for high-performance electronics. Tunneling field effect transistors based on III-V materials are demonstrated. Cryogenic applications are promising for III-V electronics enabling ultra-low power devices. Abstract: In this work, we review progress in III-V transistor technologies. Key approaches for silicon integration are described, with a distinction being made between large area layer transfer and selective growth techniques. We show how the integration approach must be tailored for the intended application to maximize performance, functionality and minimize cost. We also highlight performance boosters such as heterostructure channel stacks, which offer increased carrier mobility towards improved RF and RF-CMOS performance. Recent progress in tunneling field-effect transistors (TFETs) have enabled the TFET architecture as a process module, allowing for dense integration with MOSFETs on the same chip towards an extremely low-power CMOS technology. Finally, we highlight emerging applications for III-V devices at cryogenic temperatures, where there is a rising need for low-power electronics to support the scaling of quantum computers. The unique properties of III-V, their high mobility and band gap engineering make them highly suitable for this application.