Revisited parasitic bipolar effect in FDSOI MOSFETs: Mechanism, gain extraction and circuit applications. (November 2021)

• Record Type: Journal Article
• Authors: Wang, G.Q.; Liu, F.Y.; Li, B.; Luo, J.J.; Huang, Y.; Su, X.H.; Han, Z.S.; Zhang, J.J.; Wang, Y.C.; Wu, C.N.; Zhang, J.M.; Cristoloveanu, S.
• Is Part Of: Solid-state electronics. Volume 185(2021)
• Publication Date: 2021-11
• Subjects: Parasitic bipolar gain -- Band-to-band tunneling -- Impact ionization -- Back-gate -- FD-SOI -- Leakage power; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2021.108069
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: The PBE in FDSOI transistors is revisited including impact ionization and band-to-band tunneling. The impact of PBE on the power consumption and performance of SRAM circuits is studied. A strategy to counter PBE is proposed based on the power analysis of 6T SRAM with back-gate modulation. Abstract: The parasitic bipolar effect in fully-depleted (FD) silicon-on-insulator (SOI) transistors is revisited including impact ionization and band-to-band tunneling. We tested the transfer characteristic curves for different temperature and drain voltage, combined with TCAD simulation to analyze the dominant mechanism of parasitic bipolar transistor (PBT). In addition, the influence of gate length on PBT has also been analyzed. The current gain β of the PBT was measured at different temperatures and drain voltages. Back-gate biasing was demonstrated to efficiently suppress the bipolar amplification. TCAD simulations showed that the parasitic bipolar effect enhanced the leakage power in circuits. A strategy to counter its effect is proposed based on the power analysis of 6 T SRAM cell with back-gate modulation.