Fabrication and modeling of SiGe and Ge nanowires on insulator by three-dimensional Ge condensation method. (29th October 2019)

• Record Type: Journal Article
• Authors: Lin, Guangyang; Liang, Dongxue; Yu, Chunyu; Hong, Haiyang; Mao, Yichen; Li, Cheng; Chen, Songyan; Zeng, Yuping
• Is Part Of: Semiconductor science and technology. Volume 34:Number 12(2019)
• Publication Date: 2019-10-29
• Subjects: three-dimensional Ge condensation -- geometry factor -- low-dimensional SiGe/Ge-on-insulator; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1361-6641/ab4a29
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: In this work, three-dimensional (3D) Ge condensation was carried out to explore the merits of Ge condensation method in fabricating low-dimensional SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) structures. Through varying the width of SGOI wires from 220 nm to 50 μ m before Ge condensation, the Ge content of SiGe wires can be easily modulated from 1.0 to 0.55 after 3D Ge condensation facilitating fabrication of SiGe/Ge heterojunction nanowires (NWs). Based on the volume change of Si, Ge and SiO2 with consideration of a geometry factor, a simple 3D Ge condensation model was built. It is found that the enrichment of Ge content mainly comes from condensation effect along directions with small dimensions. The proposed 3D condensation model can be a guidance to design and fabricate low-dimensional SGOI, GOI and even SiGe/Ge heterostructures on insulator materials.