Optimization of a MOS–IGBT–SCR ESD protection component in smart power SOI technology. Issue 9 (August 2015)

• Record Type: Journal Article
• Authors: Arbess, H.; Bafleur, M.; Trémouilles, D.; Zerarka, M.
• Is Part Of: Microelectronics and reliability. Volume 55:Issue 9/10(2015)
• Page Start: 1476
• Page End: 1480
• Publication Date: 2015-08
• Subjects: ESD -- Latchup -- MOS -- IGBT -- SCR -- Holding current -- Holding voltage -- Robustness; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2015.06.138
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: A MOS–IGBT–SCR component that was proposed in a previous paper to increase the device robustness and the cost of ESD protection circuit is optimized in this paper. In order to improve its latch-up immunity, several variations of geometrical parameters that have been simulated using TCAD Sentaurus Device in another previous paper have been implemented and compared in this work. The drift area, the form factor, and the proportion of P + sections inserted into the drain are the main parameters, which have a significant impact on the latch-up immunity. TLP characterization, and curve tracer measurements have been carried out to evaluate the proposed solution. Holding current increases up to 70 mA and holding voltage up to 10 V. Highlights: We improved the behavior (latch-up control) of ESD protection components already proposed (MOS–IGBT–SCR). We have used a geometrical parameters to co control the Latch-up Immunity. After each modification, we extract the holding current, the holding voltage and the Robustness of components.