Modeling of the degradation of CMOS inverters under pulsed stress conditions from 'on-the-fly' measurements. (October 2021)

• Record Type: Journal Article
• Authors: Crespo-Yepes, A.; Ramos, R.; Barajas, E.; Aragones, X.; Mateo, D.; Martin-Martinez, J.; Rodriguez, R.; Nafria, M.
• Is Part Of: Solid-state electronics. Volume 184(2021)
• Publication Date: 2021-10
• Subjects: CMOS technology -- 'On-the-fly' stress characterization -- Circuit performance degradation -- Transistor aging -- CMOS inverters -- Measurement technique -- Analytical modelling; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2021.108094
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: In this work, an 'on-the-fly' measurement technique for the monitoring of CMOS inverters performance degradation is presented. This technique allows the characterization of the circuit degradation simultaneously with the applications of the stress. In our experiments, the inversion voltage (VINV ) shifts measured during the application of pulsed voltage stresses at the input. It is demonstrated that the shifts can be described by a power law that accounts for the stress time and voltage dependences. Moreover, the circuit degradation has been correlated to the NMOS and PMOS degradations. The results show that the degradation of the CMOS inverter can be evaluated from an analytical equation that considers only the shifts of two parameters (threshold voltage VTH, and mobility µ) of the two transistors in the inverter.