Mitigation of process variability effects using decoupling cells. (September 2019)

• Record Type: Journal Article
• Authors: Zimpeck, A.L.; Meinhardt, C.; Artola, L.; Hubert, G.; Kastensmidt, F.L.; Reis, R.A.L.
• Is Part Of: Microelectronics and reliability. Volume 100/101(2019)
• Publication Date: 2019-09
• Subjects: FinFET technology -- Reliability -- Layout level -- Process variability -- Mitigation; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2019.113446
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: From a design standpoint, the adoption of reliability-oriented approaches is crucial to improving the manufacturing yield, mainly at nanotechnologies with considerable process variability and susceptibility to radiation effects. This work shows how the use of decoupling cells with three fins on 7-nm FinFET layouts can mitigate the process variability up to 10.7% considering 3% and 5% of work-function fluctuations. Moreover, the process variability robustness can be 15.5% improved with the adoption of larger decoupling cells. Highlights: Circuit-level design approaches need to be adopted to mitigate the effects of process variations on nanotechnologies. This work explores the use of decoupling cells as a favorable technique to increase the process variability robustness. Process variability robustness rises by up to 10.7% connecting decoupling cells with three fins in the gate output. Process variability mitigation can reach 15.5% if larger decoupling cells are used. The use of transistor reordering with decoupling cells is not directly related to improving the process variation robustness.