Stress and Recovery Dynamics of Drain Current in GaN HD-GITs Submitted to DC Semi-ON stress. (September 2019)

• Record Type: Journal Article
• Authors: Padovan, V.; Koller, C.; Pobegen, G.; Ostermaier, C.; Pogany, D.
• Is Part Of: Microelectronics and reliability. Volume 100/101(2019)
• Publication Date: 2019-09
• Subjects: Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2019.113482
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: Stress and recovery dynamics of the drain current are analysed in normally-off GaN Hybrid-Drain - embedded Gate Injection Transistors (HD-GITs) submitted to a semi-ON state stress. Under this condition moderate drain current and high drain voltage (350-650 V) are applied simultaneously. During the stress phase the drain current shows a remarkable decrease due to hot carrier trapping and is dependent on the applied drain voltage, stress current and temperature (30–190 °C). This degradation is fully recoverable, either thermally in the temperature range 150–190 °C or by hole injection from the gate. We provide a model for the detrapping time constant taking into account both the thermally-driven process dominating for gate biases V GS < 3 V and hole capture dominant for V GS > 3 V. Highlights: DC semi-ON stress in HD-GITs is carried out. Drain Current Dynamics for stress and recovery are presented. The influence of bias, current and temperature for the stress is analysed. The recovery is induced by the combination of a thermal and a hole-capture process.