Retention enhancement through capacitance-dependent voltage division analysis in 3D stackable TaOx/HfO2-based selectorless memristor. (September 2021)

• Record Type: Journal Article
• Authors: Sung, Ji Hoon; Park, Ju Hyun; Jeon, Dong Su; Kim, Donghyun; Yu, Min Ji; Khot, Atul C.; Dongale, Tukaram D.; Kim, Tae Geun
• Is Part Of: Materials & design. Volume 207(2021)
• Publication Date: 2021-09
• Subjects: Bilayer memristor -- Self-rectifying -- Multilevel memory -- Crossbar array -- Nonvolatile memory; Materials -- Periodicals; Engineering design -- Periodicals; Matériaux -- Périodiques; Conception technique -- Périodiques; Electronic journals; 620.11
• DOI: 10.1016/j.matdes.2021.109845
• Languages: English
• ISSNs: 0264-1275

Abstract

Graphical abstract: Highlights: TaOx /HfO2 -based multilevel memristor optimized by capacitive voltage divider method. Selectively formed filaments in HfO2 switching layer reduce data loss of the cell. Memristor shows high retention, on/off & rectifying ratio, and endurance properties. Abstract: Sneak path current generated by adjacent cells in three-dimensional (3D) memristor arrays must be curbed while securing the multi-bit storage capability of each cell to aid in the cost-effective increase in array size. For this purpose, a 3D stackable TaOx /HfO2 -based selectorless memristor has been proposed and optimized via capacitance-dependent voltage division analysis. The proposed device utilizes the formation or rupture of conductive filaments for self-rectifying resistive switching operation, in contrast to nonfilamentary devices that often exploit the change in the charge state of the electron trap. This approach enables the reduction of the trapped charge leakage through the interface between the resistive switching and metal layers effectively, giving rise to excellent retention properties (>5 × 10 5 s). Furthermore, the proposed device exhibits a sufficiently high on/off ratio (~1.35 × 10 3 ), rectification ratio (~2.3 × 10 3 ), endurance (1.5 × 10 2 cycles), and low resistance variation (standard deviation <0.022). Moreover, multilevel operations are facilitated, making the proposed device suitable for high-density, nonvolatile memory applications.