Current-to-transconductance ratio technique for simultaneous extraction of threshold voltage and parasitic resistances in MOSFETs. (September 2021)

• Record Type: Journal Article
• Authors: Kim, Haesung; Yoo, Han Bin; Ryu, Ji Hee; Bae, Jong-Ho; Choi, Sung-Jin; Kim, Dae Hwan; Kim, Dong Myong
• Is Part Of: Solid-state electronics. Volume 183(2021)
• Publication Date: 2021-09
• Subjects: Parasitic resistance -- Separate extraction -- Threshold voltage -- Source resistance -- Drain resistance -- MOSFET; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2021.108133
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: Simple technique for simultaneously extracting R D, R S, and V T of MOSFET is presented. This technique is applicable to any single MOSFET with CLM and structural asymmetry. The validity of the proposed technique is demonstrated experimentally. Abstract: In this work, a current-to-transconductance ratio technique is proposed for simultaneous extraction of the threshold voltage ( V T ) and parasitic source ( R S ) and drain ( R D ) resistances in short channel metal–oxide–semiconductor field-effect transistors (MOSFETs). The proposed technique allows simultaneous extraction of R S, R D, and V T in any single MOSFET with the channel length modulation (CLM) and the structural asymmetry. The proposed method is experimentally verified through Si MOSFETs with intentional asymmetry by connecting an external resistor ( R ext ) to the source terminal. We experimentally confirmed that extracted R S, R D, and V T are independent of the drain bias ( V DS ) and intentional R ext employed for the asymmetry. We also compared the results with previously reported techniques.