Referenceless single‐loop CDR with a half‐rate linear PD and frequency acquisition technique. Issue 5 (1st March 2020)

• Record Type: Journal Article
• Authors: Kim, H.R.; Chun, J.‐H.
• Is Part Of: Electronics letters. Volume 56:Issue 5(2020)
• Page Start: 237
• Page End: 239
• Publication Date: 2020-03-01
• Subjects: phase detectors -- CMOS integrated circuits -- clock and data recovery circuits -- jitter; referenceless single‐loop CDR -- half‐rate linear PD -- referenceless single‐loop clock -- clock and data recovery circuit -- half‐rate linear phase detector -- frequency‐tracking unit -- cycle‐slip detector -- high frequency jitter tolerance -- phase‐tracking loop -- frequency acquisition technique -- power 26.0 mW -- voltage 1.0 V; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2019.3075
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A referenceless single‐loop clock and data recovery (CDR) circuit with a half‐rate linear phase detector (PD) and an inherent frequency acquisition technique are introduced. Cycle‐slip in the half‐rate linear PD and its relationship with the frequency acquisition are described in detail. The single‐loop CDR consists of a conventional phase‐tracking loop and a frequency‐tracking unit, referred to as the cycle‐slip detector. The proposed CDR is fabricated in a 28 nm CMOS process and achieves a wide capture range of 2.6 Gb/s for a PRBS31 pattern. The RMS and peak‐to‐peak jitter of the recovered clock are 2.40 ps rms and 21.4 ps pp, respectively, at 8 Gb/s. The high frequency jitter tolerance is measured as 0.3 UI pp . The CDR occupies 0.105 mm 2 and consumes 26 mW at 8 Gb/s from a 1.0 V supply.