Referenceless single‐loop CDR with a half‐rate linear PD and frequency acquisition technique. Issue 5 (1st March 2020) - Kim, H.R.; Chun, J.‐H.
Abstract : A referenceless single‐loop clock and data recovery (CDR) circuit with a half‐rate linear phase detector (PD) and an inherent frequency acquisition technique are introduced. Cycle‐slip in the half‐rate linear PD and its relationship with the frequency acquisition are described in detail. The single‐loop CDR consists of a conventional phase‐tracking loop and a frequency‐tracking unit, referred to as the cycle‐slip detector. The proposed CDR is fabricated in a 28 nm CMOS process and achieves a wide capture range of 2.6 Gb/s for a PRBS31 pattern. The RMS and peak‐to‐peak jitter of the recovered clock are 2.40 ps rms and 21.4 ps pp, respectively, at 8 Gb/s. The high frequency jitter tolerance is measured as 0.3 UI pp . The CDR occupies 0.105 mm 2 and consumes 26 mW at 8 Gb/s from a 1.0 V supply.