Design topologies with dual‐Vth and dual‐Tox assignment in 16 nm CMOS technology. Issue 4 (30th April 2020)

• Record Type: Journal Article
• Authors: Singhal, Smita; Mehra, Anu; Tripathi, Upendra
• Is Part Of: IET computers & digital techniques. Volume 14:Issue 4(2020)
• Page Start: 176
• Page End: 186
• Publication Date: 2020-04-30
• Subjects: low‐power electronics -- leakage currents -- CMOS logic circuits -- adders -- circuit optimisation -- logic design -- integrated circuit design -- network topology; adder circuit -- direct topology -- design topologies -- CMOS technology -- dual threshold voltage -- dual gate oxide thickness -- complementary metal‐oxide‐semiconductor technology -- static power dissipation -- power‐delay‐product -- dual‐Tox assignment -- dual‐Vth assignment -- leakage reduction -- supply switching with ground collapse -- SSGC techniques -- high‐performance applications -- low power applications -- circuit optimisation -- size 16.0 nm -- word length 1 bit; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2018.5211
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : This study presents different topologies for the assignment of dual threshold voltage and dual gate oxide thickness in 16 nm complementary metal‐oxide‐semiconductor technology. The objective is to optimise the circuit in terms of static power dissipation, delay, and power‐delay‐product (pdp). Topologies namely direct, grouping, and divide‐by‐2 are simulated for ( A + B ) ⋅ C ¯ and conventional 1‐bit full adder circuits. Results of the proposed topologies are compared with some of the existing techniques of leakage reduction i.e. dual‐ V th, dual‐ T ox and supply switching with ground collapse (SSGC). 1‐bit full adder circuit using direct topology reduces static power to 99.98, 96.71, and 95.86% as compared to static power in dual‐ V th, dual‐ T ox, and SSGC techniques, respectively. The pdp of the circuit is significantly improved using proposed topologies. Thus, these topologies can be used for low power and high‐performance applications with no area overhead.