Design topologies with dual‐Vth and dual‐Tox assignment in 16 nm CMOS technology. Issue 4 (30th April 2020) - Singhal, Smita; Mehra, Anu; Tripathi, Upendra
Abstract : This study presents different topologies for the assignment of dual threshold voltage and dual gate oxide thickness in 16 nm complementary metal‐oxide‐semiconductor technology. The objective is to optimise the circuit in terms of static power dissipation, delay, and power‐delay‐product (pdp). Topologies namely direct, grouping, and divide‐by‐2 are simulated for ( A + B ) ⋅ C ¯ and conventional 1‐bit full adder circuits. Results of the proposed topologies are compared with some of the existing techniques of leakage reduction i.e. dual‐ V th, dual‐ T ox and supply switching with ground collapse (SSGC). 1‐bit full adder circuit using direct topology reduces static power to 99.98, 96.71, and 95.86% as compared to static power in dual‐ V th, dual‐ T ox, and SSGC techniques, respectively. The pdp of the circuit is significantly improved using proposed topologies. Thus, these topologies can be used for low power and high‐performance applications with no area overhead.