9‐bit time–digital‐converter‐assisted compressive‐sensing analogue–digital‐converter with 4 GS/s equivalent speed. Issue 6 (1st March 2016)

• Record Type: Journal Article
• Authors: Hu, B.; Ren, F.; Chen, Z.‐Z.; Jiang, X.; Chang, M.‐C.F.
• Is Part Of: Electronics letters. Volume 52:Issue 6(2016)
• Page Start: 430
• Page End: 432
• Publication Date: 2016-03-01
• Subjects: time‐digital conversion -- compressed sensing -- analogue‐digital conversion -- comparators (circuits) -- CMOS digital integrated circuits; time–digital‐converter‐assisted compressive‐sensing analogue–digital‐converter -- TDC -- CS operation -- energy‐efficient high‐speed compressive‐sensing -- voltage‐time‐converter -- cross‐domain residue conveyer -- two‐stage self‐timed pipeline ADC architecture -- voltage‐domain comparator‐interleaved SAR ADC front‐end -- two‐dimensional Vernier TDC back‐end -- CMOS technology -- CS‐enabled sub‐Nyquist operation -- hybrid quantisation scheme -- word length 9 bit -- size 65 nm; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2015.3778
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A novel 9‐bit time–digital‐converter (TDC)‐assisted analogue–digital‐converter (ADC) supporting energy‐efficient high‐speed compressive‐sensing (CS) operation is presented. With a voltage–time‐converter serving as the cross‐domain residue conveyer, the proposed two‐stage self‐timed pipeline ADC architecture hybrids a voltage‐domain comparator‐interleaved successive‐approximation (SAR) ADC front‐end and a time‐domain locally readjusted folding two‐dimensional Vernier TDC back‐end. Implemented in 65 nm CMOS technology, the prototype benefits from both the CS‐enabled sub‐Nyquist operation and the hybrid quantisation scheme, leading up to 4 GS/s equivalent speed with 34.2 dB signal‐noise‐distortion‐ratio (SNDR) and a figure‐of‐merit (FOM) of 101 fJ/conversion step.