9‐bit time–digital‐converter‐assisted compressive‐sensing analogue–digital‐converter with 4 GS/s equivalent speed. Issue 6 (1st March 2016) - Hu, B.; Ren, F.; Chen, Z.‐Z.; Jiang, X.; Chang, M.‐C.F.
Abstract : A novel 9‐bit time–digital‐converter (TDC)‐assisted analogue–digital‐converter (ADC) supporting energy‐efficient high‐speed compressive‐sensing (CS) operation is presented. With a voltage–time‐converter serving as the cross‐domain residue conveyer, the proposed two‐stage self‐timed pipeline ADC architecture hybrids a voltage‐domain comparator‐interleaved successive‐approximation (SAR) ADC front‐end and a time‐domain locally readjusted folding two‐dimensional Vernier TDC back‐end. Implemented in 65 nm CMOS technology, the prototype benefits from both the CS‐enabled sub‐Nyquist operation and the hybrid quantisation scheme, leading up to 4 GS/s equivalent speed with 34.2 dB signal‐noise‐distortion‐ratio (SNDR) and a figure‐of‐merit (FOM) of 101 fJ/conversion step.