Soft‐error reliable architecture for future microprocessors. Issue 3 (5th March 2019)

• Record Type: Journal Article
• Authors: Gopalakrishnan, Shoba; Singh, Virendra
• Is Part Of: IET computers & digital techniques. Volume 13:Issue 3(2019)
• Page Start: 233
• Page End: 242
• Publication Date: 2019-03-05
• Subjects: redundancy -- fault tolerant computing -- security of data -- fault tolerance -- integrated circuit reliability -- microprocessor chips -- instruction sets; soft‐error reliable architecture -- future microprocessors -- transient error -- transient hardware faults -- high‐energy particles -- neutron -- alpha particle strikes -- fault‐tolerant architecture -- hardware‐based solution -- REMO -- time redundancy -- high fault coverage -- minimum overheads -- REMORA -- software approaches -- fault tolerance -- persistent issue -- unprotected code -- simulation results -- SPEC2006 benchmark suite -- power overhead -- redundant execution -- negligible performance penalty -- fault‐free run -- performance degradation increases -- code size inflation; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2018.5015
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : The transient error is the failure of the device due to transient hardware faults caused by high‐energy particles like neutron and alpha particle strikes. In this study, the authors propose two schemes of fault‐tolerant architecture. The first scheme is a hardware‐based solution called REMO that combines the best features of space and time redundancy. REMO provides very high fault coverage with minimum overheads in performance, power and area. The second scheme, REMORA combines the best features of hardware and software approaches of fault tolerance. The persistent issue of unprotected code which exists in software approaches is eliminated in this proposal. Simulation results from a SPEC2006 benchmark suite indicate, REMO incurs an increase in the area of about 6%, power overhead is 9% in spite of redundant execution and a negligible performance penalty during a fault‐free run. In REMORA, performance degradation increases to 12%. The code size inflation is close to 12%. This is due to the additional signature instructions inserted into the application program. In this study, the authors have explored the possibility of eliminating this penalty by embedding the signatures in control flow instructions. The power and area overhead of REMORA is on par with REMO.