Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics. (22nd April 2012)

• Record Type: Journal Article
• Authors: Mukhopadhyay, Joyjit; Pandit, Soumya
• Other Names: Chen Chien-In Henry Academic Editor.
• Is Part Of: VLSI design. Volume 2012(2012)
• Publication Date: 2012-04-22
• Subjects: Integrated circuits -- Very large scale integration -- Periodicals; 621.395
• DOI: 10.1155/2012/505983
• Languages: English
• ISSNs: 1065-514X

Abstract

Abstract : This paper presents a technique for the modeling and design of a nano scale CMOS inverter circuit using artificial neural network and particle swarm optimization algorithm such that the switching characteristics of the circuit is symmetric, that is, has nearly equal rise and fall time and equal output high-to-low and low-to-high propagation delay. The channel width of the transistors and the load capacitor value are taken as design parameters. The designed circuit has been implemented at the transistor-level and simulated using TSPICE for 45 nm process technology. The PSO-generated results have been compared with SPICE results. A very good accuracy has been achieved. In addition, the advantage of the present approach over an existing approach for the same purpose has been demonstrated through simulation results.