The Impact of Statistical Leakage Models on Design Yield Estimation. (22nd February 2011)

• Record Type: Journal Article
• Authors: Kanj, Rouwaida; Joshi, Rajiv; Nassif, Sani
• Other Names: Hu Shiyan Academic Editor.
• Is Part Of: VLSI design. Volume 2011(2011)
• Publication Date: 2011-02-22
• Subjects: Integrated circuits -- Very large scale integration -- Periodicals; 621.395
• DOI: 10.1155/2011/471903
• Languages: English
• ISSNs: 1065-514X

Abstract

Abstract : Device mismatch and process variation models play a key role in determining the functionality and yield of sub-100 nm design. Average characteristics are often of interest, such as the average leakage current or the average read delay. However, detecting rare functional fails is critical for memory design and designers often seek techniques that enable accurately modeling such events. Extremely leaky devices can inflict functionality fails. The plurality of leaky devices on a bitline increase the dimensionality of the yield estimation problem. Simplified models are possible by adopting approximations to the underlying sum of lognormals. The implications of such approximations on tail probabilities may in turn bias the yield estimate. We review different closed form approximations and compare against the CDF matching method, which is shown to be most effective method for accurate statistical leakage modeling.