Cite
HARVARD Citation
Ibrahim, A. (2021). Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2m). IET computers & digital techniques. 15 (3), pp. 223-229. [Online].
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Ibrahim, A. (2021). Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2m). IET computers & digital techniques. 15 (3), pp. 223-229. [Online].