Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2m). Issue 3 (10th March 2021)

• Record Type: Journal Article
• Authors: Ibrahim, Atef
• Is Part Of: IET computers & digital techniques. Volume 15:Issue 3(2021)
• Page Start: 223
• Page End: 229
• Publication Date: 2021-03-10
• Subjects: Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/cdt2.12026
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract: This article offers a new bit‐serial systolic array architecture to implement the interleaved multiplication algorithm in the binary‐extended field. The exhibited multiplier structure is more proper for VLSI implementation as it has regular cell structures as well as local communication wires between the cells. The ASIC implementation results of the suggested bit‐serial multiplier structure and the existing competitive bit‐serial multiplier structures previously described in the literature indicate that the recommended design achieves a notable reduction in area and significant improvement of area‐time complexities by at least 28.4% and 35.7%, respectively. Therefore, it is more proper for cryptographic applications forcing more restrictions on the space.