Error Immune Logic for Low-Power Probabilistic Computing. (28th February 2010)

• Record Type: Journal Article
• Authors: Marr, Bo; George, Jason; Degnan, Brian; Anderson, David V.; Hasler, Paul
• Other Names: Peterson Gregory D. Academic Editor.
• Is Part Of: VLSI design. Volume 2010(2010)
• Publication Date: 2010-02-28
• Subjects: Integrated circuits -- Very large scale integration -- Periodicals; 621.395
• DOI: 10.1155/2010/460312
• Languages: English
• ISSNs: 1065-514X

Abstract

Abstract : Two novel theorems are developed which prove that certain logic functions are more robust to errors than others. These theorems are used to construct datapath circuits that give an increased immunity to error over other naive implementations. A link between probabilistic operation and ultra-low energy computing has been shown in prior work. These novel theorems and designs will be used to further improve probabilistic design of ultra-low power datapaths. This culminates in an asynchronous design for the maximum amount of energy savings per a given error rate. Spice simulation results using a commercially available and well-tested 0.25 μ m technology are given verifying the ultra-low power, probabilistic full-adder designs. Further, close to 6X energy savings is achieved for a probabilistic full-adder over the deterministic case.